Thursday, 5 January 2017

555 Timer Tutorial

The 555 timer IC is an integrated circuit (chip) used in a variety of timer, pulse generation, and oscillator applications. The 555 can be used to provide time delays, as an oscillator, and as a flip-flop element. Derivatives provide two or four timing circuits in one package.
Introduced in 1972 by Signetics, the 555 is still in widespread use due to its low price, ease of use, and stability. It is now made by many companies in the original bipolar and in low-power CMOS. As of 2003, it was estimated that 1 billion units were manufactured every year. The 555 is the most popular integrated circuit ever manufactured

555 Timer Block Diagram

•    Pin 1. – Ground, The ground pin connects the 555 timer to the negative (0v) supply rail.
• • Pin 2. – Trigger, The negative input to comparator No 1. A negative pulse on this pin “sets” the internal Flip-flop when the voltage drops below 1/3Vcc causing the output to switch from a “LOW” to a “HIGH” state.
• • Pin 3. – Output, The output pin can drive any TTL circuit and is capable of sourcing or sinking up to 200mA of current at an output voltage equal to approximately Vcc – 1.5V so small speakers, LEDs or motors can be connected directly to the output.
• • Pin 4. – Reset, This pin is used to “reset” the internal Flip-flop controlling the state of the output, pin 3. This is an active-low input and is generally connected to a logic “1” level when not used to prevent any unwanted resetting of the output.
• • Pin 5. – Control Voltage, This pin controls the timing of the 555 by overriding the 2/3Vcc level of the voltage divider network. By applying a voltage to this pin the width of the output signal can be varied independently of the RC timing network. When not used it is connected to ground via a 10nF capacitor to eliminate any noise.
• • Pin 6. – Threshold, The positive input to comparator No 2. This pin is used to reset the Flip-flop when the voltage applied to it exceeds 2/3Vcc causing the output to switch from “HIGH” to “LOW” state. This pin connects directly to the RC timing circuit.
• • Pin 7. – Discharge, The discharge pin is connected directly to the Collector of an internal NPN transistor which is used to “discharge” the timing capacitor to ground when the output at pin 3 switches “LOW”.
• • Pin 8. – Supply +Vcc, This is the power supply pin and for general purpose TTL 555 timers is between 4.5V and 15V.

Monostable

The output pulse ends when the voltage on the capacitor equals 2/3 of the supply voltage. The output pulse width can be lengthened or shortened to the need of the specific application by adjusting the values of R and C.
The output pulse width of time t, which is the time it takes to charge C to 2/3 of the supply voltage, is given by
${\displaystyle t=\ln(3)\cdot RC\approx 1.1RC}$
where t is in seconds, R is in ohms (resistance) and C is in farads (capacitance).
While using the timer IC in monostable mode, the main disadvantage is that the time span between any two triggering pulses must be greater than the RC time constant. Conversely, ignoring closely spaced pulses is done by setting the RC time constant to be larger than the span between spurious triggers. (Example: ignoring switch contact bouncing.)

Astable

Schematic of a 555 in astable mode
In astable mode, the 555 timer puts out a continuous stream of rectangular pulses having a specified frequency. Resistor R1 is connected between VCC and the discharge pin (pin 7) and another resistor (R2) is connected between the discharge pin (pin 7), and the trigger (pin 2) and threshold (pin 6) pins that share a common node. Hence the capacitor is charged through R1 and R2, and discharged only through R2, since pin 7 has low impedance to ground during output low intervals of the cycle, therefore discharging the capacitor.
In the astable mode, the frequency of the pulse stream depends on the values of R1, R2 and C:
${\displaystyle f={\frac {1}{\ln(2)\cdot C\cdot (R_{1}+2R_{2})}}}$
The high time from each pulse is given by:
${\displaystyle \mathrm {high} =\ln(2)\cdot C\cdot (R_{1}+R_{2})}$
and the low time from each pulse is given by:
${\displaystyle \mathrm {low} =\ln(2)\cdot C\cdot R_{2}}$
where R1 and R2 are the values of the resistors in ohms and C is the value of the capacitor in farads.
The power capability of R1 must be greater than ${\displaystyle {\frac {V_{cc}^{2}}{R_{1}}}}$.
Particularly with bipolar 555s, low values of ${\displaystyle R_{1}}$ must be avoided so that the output stays saturated near zero volts during discharge, as assumed by the above equation. Otherwise the output low time will be greater than calculated above. The first cycle will take appreciably longer than the calculated time, as the capacitor must charge from 0V to 2/3 of VCC from power-up, but only from 1/3 of VCC to 2/3 of VCC on subsequent cycles.
To have an output high time shorter than the low time (i.e., a duty cycle less than 50%) a small diode (that is fast enough for the application) can be placed in parallel with R2, with the cathode on the capacitor side. This bypasses R2 during the high part of the cycle so that the high interval depends only on R1 and C, with an adjustment based the voltage drop across the diode. The voltage drop across the diode slows charging on the capacitor so that the high time is a longer than the expected and often-cited ln(2)*R1C = 0.693 R1C. The low time will be the same as above, 0.693 R2C. With the bypass diode, the high time is
${\displaystyle \mathrm {high} =R_{1}\cdot C\cdot \ln \left({\frac {2V_{\textrm {cc}}-3V_{\textrm {diode}}}{V_{\textrm {cc}}-3V_{\textrm {diode}}}}\right)}$
where Vdiode is when the diode's "on" current is 1/2 of Vcc/R1 which can be determined from its datasheet or by testing. As an extreme example, when Vcc= 5 and Vdiode= 0.7, high time = 1.00 R1C which is 45% longer than the "expected" 0.693 R1C. At the other extreme, when Vcc= 15 and Vdiode= 0.3, the high time = 0.725 R1C which is closer to the expected 0.693 R1C. The equation reduces to the expected 0.693 R1C if Vdiode= 0.
The operation of RESET in this mode is not well-defined. Some manufacturers' parts will hold the output state to what it was when RESET is taken low, others will send the output either high or low.
The astable configuration, with two resistors, cannot produce a 50% duty cycle. To produce a 50% duty cycle, eliminate R1, disconnect pin 7 and connect the supply end of R2 to pin 3, the output pin. This circuit is similar to using an inverter gate as an oscillator, but with fewer components than the astable configuration, and a much higher power output than a TTL or CMOS gate. The duty cycle for either the 555 or inverter-gate timer will not be precisely 50% and will change based off any load that the output is also driving while high (longer duty cycles for greater loads) due to the fact the timing network is supplied from the devices output pin, which has different internal resistances depending on whether it is in the high or low state (high side drivers tend to be more resistive).